1. Field of the Invention
The present invention relates to the protection of integrated circuits against electrostatic discharges.
2. Discussion of the Related Art
An integrated circuit comprises metal pads intended to provide connections to the outside. Some of the pads are capable of receiving power supply voltages. The other pads are capable of receiving and/or of providing input/output signals. Power supply rails, connected to the supply pads, are generally provided all around the circuit to power its different components. Generally, an insulating layer covers the circuit, only leaving access to the metal pads.
Such a circuit generally receives and/or delivers signals of low voltage level (for example, from 1 to 5 V) and of low current intensity (for example, from 1 μA to 10 mA), and may be damaged when overvoltages or overintensities occur between pads of the circuit.
It is thus provided to associate a protection structure with each pad. The protection structure should be able to rapidly drain off significant currents, that appear when an electrostatic discharge occurs on an input/output pad (“pad”, for simplification) or on a pad connected to a power supply rail (“rail”, for simplification).
FIG. 1 shows an example of a protection structure 1 associated with an integrated circuit input/output pad 3. A diode 5 is forward connected between pad 3 and a high power supply rail VDD. A diode 7 is reverse-connected between pad 3 and a low power supply rail VSS. A MOS transistor 9, used as a switch, is connected between high and low power supply rails VDD and VSS. An overvoltage detection circuit 11, connected in parallel with MOS transistor 9, provides a trigger signal to this transistor. MOS transistor 9 comprises a parasitic diode 10, forward connected between rail VSS and rail VDD.
In normal operation, when the chip is powered, the signals on pad 3 and rails VDD and VSS are such that diodes 5 and 7 conduct no current and detection circuit 11 makes MOS transistor 9 non-conductive.
In case of a positive overvoltage between rails VDD and VSS, circuit 11 turns on transistor 9, which enables to remove the overvoltage.
In case of a negative overvoltage between rails VDD and VSS, parasitic diode 10 of transistor 9 becomes conductive and the overvoltage is removed.
In case of a positive overvoltage between pad 3 and high power supply rail VDD, diode 5 becomes conductive and the overvoltage is removed.
In case of a negative overvoltage between pad 3 and rail VDD, circuit 11 turns on transistor 9 and the overvoltage is removed through transistor 9 and diode 7.
In case of a positive overvoltage between pad 3 and rail VSS, diode 5 becomes conductive and the positive overvoltage is transferred onto rail VDD, which corresponds to the above case of a positive overvoltage between rails VDD and VSS.
In case of a negative overvoltage between pad 3 and rail VSS, diode 7 becomes conductive and the overvoltage is removed.
In case of a positive or negative overvoltage between two input/output pads 3, diodes 5 or 7 associated with the concerned pads become conductive, and the overvoltage is transferred onto high and low power supply rails VDD and VSS. This corresponds to one of the above overvoltage cases.
FIG. 2 partly shows the diagram of FIG. 1 and shows in further detail an example of a possible embodiment of a circuit 11 for detecting a positive overvoltage between rails VDD and VSS, and for controlling protection transistor 9. An edge detector, formed of a resistor 21 in series with a capacitor 23, is connected between power supply rails VDD and VSS. Node M between resistor 21 and capacitor 23 is connected to the gate of a P-channel MOS transistor 25 having its source connected to rail VDD and having its drain connected to rail VSS via a resistor 27. Node N between the drain of transistor 25 and resistor 27 is connected to the gate of transistor 9. An assembly 29 of diodes in series is forward-connected between node M and rail VSS. In this example, assembly 29 comprises four diodes in series.
In normal operation, when the circuit is powered, node M is in a high state. P-channel MOS transistor 25 thus conducts no current. Thus, gate node N of transistor 9 is in a low state, and protection transistor 9 is maintained off. When the potential difference between rails VDD and VSS increases, the voltage of node M also increases. When the voltage of node M reaches a given threshold, diode assembly 29 becomes conductive. In this example, if each diode has a 0.6-V threshold voltage, assembly 29 becomes conductive when the voltage of node M exceeds 2.4 V. This results in a voltage drop at node M, which turns on P-channel MOS transistor 25. Thus, gate node N of protection transistor 9 switches to a high state, that is, substantially to the same positive voltage as rail VDD. Transistor 9 thus becomes conductive and the overvoltage is removed.
When the integrated circuit is not powered, node M is in a low state. Since transistor 25 is not powered, drain node N of this transistor is in an undetermined state. If an abrupt positive overvoltage (fast voltage rise) occurs between rails VDD and VSS, node M remains in a low state. Transistor 25 thus becomes conductive and node N switches to a high state. Thus, protection transistor 9 is made conductive and the overvoltage is removed.
A disadvantage of the protection structure of FIGS. 1 and 2 lies in the fact that, to be able to drain off the currents induced by electrostatic discharges, diodes 5 and 7 and transistor 9 should have a large surface area (for example, a 200-μm junction perimeter per diode and a channel width of several tens of millimeters for the transistor). As a result, a significant silicon surface area is exclusively dedicated to the protection against electrostatic discharges, to the detriment of the other circuit components. Further, due to its large size, MOS transistor 9, in the off state, is crossed by significant leakage currents, which increases the circuit power consumption and the stray capacitance between rails VDD and VSS.